MT46H16M16LFBF-6ITH Datasheet, PDF (26/79 Pages) Micron Technology – Mobile DDR SDRAM MT46H16M16LF – 4 Meg x 16 x 4 banks MT46H8M32LF/LG – 2 Meg x 32 x 4 banks

256Mb: x16, x32 Mobile DDR SDRAM
Operations
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR
SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE
command, which selects both the bank and the row to be activated, as shown in
Figure 11.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the ^tRCD specification. ^tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a ^tRCD specification of 20ns with a 133 MHz clock (7.5ns period)
results in 2.7 clocks rounded to 3. This is reflected in Figure 12 on page 27, which covers
any case where 2 < ^tRCD (MIN)/ ^tCK ≤ 3. (Figure 12 also shows the same case for ^tRRD;
the same procedure is used to convert other specification limits from time units to clock
cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by ^tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE commands to different banks is
defined by ^tRRD.
Figure 11: Activating a Specific Row in a Specific Bank
CK#
CK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0–A12
RA
BA0, BA1
BA
Notes: 1. RA = row address
2. BA = bank address
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
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