MT48LC16M16A2TG-75ITD Datasheet, PDF (66/86 Pages) Micron Technology – 256Mb: x4, x8, x16 SDRAM

256Mb: x4, x8, x16 SDRAM
WRITE Operation
Figure 39: WRITE – DQM Operation
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
Command
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
tCMS tCMH
DQM
Address
A10
BA0, BA1
tAS tAH
Row
tAS tAH
Row
tAS tAH
Bank
DQ
Column m
Enable auto precharge
Disable auto precharge
Bank
tDS tDH
D_IN
tDS tDH
D_IN
tDS tDH
D_IN
tRCD
Note: 1. For this example, BL = 4.
NOP
Don’t Care
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. S 12/12 EN
66
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