MT48LC16M16A2TG-75ITD Datasheet, PDF (62/86 Pages) Micron Technology – 256Mb: x4, x8, x16 SDRAM

Figure 35: WRITE-to-PRECHARGE
T0
CLK
t_{WR @} t_{CK ≥ 15ns}
DQM
Command
WRITE
Address
Bank a,
Col n
DQ
D_IN
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WRITE Operation
T1
T2
T3
T4
T5
T6
NOP
PRECHARGE
tRP
NOP
NOP
Bank
(a or all)
t_WR
D_IN
ACTIVE
Bank a,
Row
NOP
t_{WR @} t_{CK < 15ns}
DQM
Command
WRITE
NOP
Address
Bank a,
Col n
DQ
D_IN
D_IN
NOP
PRECHARGE
tRP
NOP
NOP
Bank
(a or all)
t _WR
ACTIVE
Bank a,
Row
Transitioning data
Don’t Care
Note: 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command is ignored. The last data written (provided that DQM is LOW at
that time) will be the input data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 36 (page 63), where data n is the last desired data
element of a longer burst.
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