MT48LC16M16A2TG-75ITD Datasheet, PDF (38/86 Pages) Micron Technology – 256Mb: x4, x8, x16 SDRAM

256Mb: x4, x8, x16 SDRAM
Truth Tables
Read with auto precharge enabled: Starts with registration of a READ command
with auto precharge enabled and ends when ^tRP has been met. After ^tRP is met, the
bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command
with auto precharge enabled and ends when ^tRP has been met. After ^tRP is met, the
bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these
states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t_{RFC is met. After} t_{RFC is met, the device will be in the all banks idle state.}
Accessing mode register: Starts with registration of a LOAD MODE REGISTER com-
mand and ends when ^tMRD has been met. After ^tMRD is met, the device will be in the
all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
when ^tRP is met. After ^tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank specific; requires that all banks are idle.
8. Does not affect the state of the bank and acts as a NOP to that bank.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
10. May or may not be bank specific; if all banks need to be precharged, each must be in a
valid state for precharging.
11. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, re-
gardless of bank.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. S 12/12 EN
38
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