MT48LC16M16A2TG-75ITD Datasheet, PDF (54/86 Pages) Micron Technology – 256Mb: x4, x8, x16 SDRAM

Figure 25: READ-to-WRITE With Extra Clock Cycle
T0
T1
T2
T3
CLK
DQM
256Mb: x4, x8, x16 SDRAM
READ Operation
T4
T5
Command
READ
NOP
NOP
NOP
NOP
WRITE
Address
Bank,
Col n
DQ
tHZ
D_OUT
Transitioning data
Bank,
Col b
D_IN
tDS
Don’t Care
Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank.
Figure 26: READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ
NOP
Address
Bank a,
Col n
NOP
NOP
PRECHARGE
tRP
NOP
X = 1 cycle
Bank
(a or all)
NOP
ACTIVE
Bank a,
Row
DQ
CL = 2
T0
T1
CLK
Command
READ
NOP
Address
Bank a,
Col
D_OUT
D_OUT
D_OUT
D_OUT
T2
T3
T4
T5
T6
NOP
NOP
PRECHARGE
t _RP
NOP
X = 2 cycles
Bank
(a or all)
NOP
T7
ACTIVE
Bank a,
Row
DQ
CL = 3
Note: 1. DQM is LOW.
D_OUT
D_OUT
D_OUT
D_OUT
Transitioning data
Don’t Care
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. S 12/12 EN
54
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