N25Q512A13GSF40F Datasheet, PDF (63/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

512Mb, Multiple I/O Serial Flash Memory
ERASE Operations
byte output. When the operation completes, the program or erase controller bit is
cleared to 1.
The command is not executed if any sector is locked. Instead, the write enable latch bit
remains set to 1, and flag status register bits 1 and 5 are set.
Figure 33: DIE ERASE Command
Extended
C
DQ0
Dual
C
DQ0[1:0]
Quad
C
DQ0[3:0]
0
7
8
Command
MSB
0
LSB
A[MAX]
3
4
Command
MSB
0
LSB
A[MAX]
1
2
MSB
Command
LSB
A[MAX]
C_x
A[MIN]
C_x
A[MIN]
C_x
A[MIN]
Note:
1. For extended SPI protocol, C_x = 7 + (A[MAX] + 1).
For dual SPI protocol, C_x = 3 + (A[MAX] + 1)/2.
For quad SPI protocol, C_x = 1 + (A[MAX] + 1)/4.
BULK ERASE Command
To initiate the BULK ERASE command, the WRITE ENABLE command must be issued
to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit
of the last data byte has been latched in, after which it must be driven HIGH. The com-
mand code is input on DQ0. When S# is driven HIGH, the operation, which is self-
timed, is initiated; its duration is ^tBE. The operation is terminated by driving S# HIGH.
If the write enable latch bit is not set, the device ignores the SECTOR ERASE command
and no error bits are set to indicate operation failure.
When the operation is in progress, the write in progress bit is set to 1 and the write ena-
ble latch bit is cleared to 0, whether the operation is successful or not. The status regis-
ter and flag status register can be polled for the operation status. When the operation
completes, the write in progress bit is cleared to 0.
If the operation times out, the write enable latch bit is reset and erase error bit is set to
1. If S# is not driven HIGH, the command is not executed, the flag status register error
bits are not set, and the write enable latch remains set to 1.
The command is not executed if any sector is locked. Instead, the write enable latch bit
remains set to 1, and flag status register bits 1 and 5 are set.
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. M 12/12 EN
63
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