N25Q512A13GSF40F Datasheet, PDF(21/91 Page) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

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N25Q512A13GSF40F Datasheet, PDF (21/91 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

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512Mb, Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Nonvolatile and Volatile Configuration Registers

Table 10: Nonvolatile Configuration Register Bit Definitions

Note 1 applies to entire table

Bit Name

Settings

15:12 Number of

dummy clock

cycles

0000 (identical to 1111)

0001

0010

1101

1110

1111

11:9 XIP mode at 000 = XIP: Fast Read

power-on re- 001 = XIP: Dual Output Fast Read

set

010 = XIP: Dual I/O Fast Read

011 = XIP: Quad Output Fast Read

100 = XIP: Quad I/O Fast Read

101 = Reserved

110 = Reserved

111 = Disabled (Default)

8:6 Output driver 000 = Reserved

strength

001 = 90 Ohms

010 = 60 Ohms

011 = 45 Ohms

100 = Reserved

101 = 20 Ohms

110 = 15 Ohms

111 = 30 (Default)

5 Reserved

4 Reset/hold

0 = Disabled

1 = Enabled (Default)

3 Quad I/O pro- 0 = Enabled

tocol

1 = Disabled (Default, Extended SPI pro-

tocol)

2 Dual I/O pro- 0 = Enabled

tocol

1 = Disabled (Default, Extended SPI pro-

tocol)

1 128Mb seg- 0 = Upper 128Mb segment

ment select 1 = Lower 128Mb segment (Default)

0 Address bytes 0 = Enable 4B address

1 = Enable 3B address (Default)

Description

Notes

Sets the number of dummy clock cycles subse-

2, 3

quent to all FAST READ commands.

The default setting targets the maximum al-

lowed frequency and guarantees backward com-

patibility.

Enables the device to operate in the selected XIP

mode immediately after power-on reset.

Optimizes impedance at VCC/2 output voltage.

"Don't Care."

Enables or disables hold or reset.

(Available on dedicated part numbers.)

Enables or disables quad I/O protocol.

Enables or disables dual I/O protocol.

Selects a 128Mb segment as default for 3B ad-

dress operations. See also the extended address

Defines the number of address bytes for a com-

mand.

Notes:

1. Settings determine device memory configuration after power-on. The device ships from

the factory with all bits erased to 1 (FFFFh). The register is read from or written to by

READ NONVOLATILE CONFIGURATION REGISTER or WRITE NONVOLATILE CONFIGURA-

TION REGISTER commands, respectively.

PDF: 09005aef84752721

n25q_512mb_1ce_3V_65nm.pdf - Rev. M 12/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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