MT46V128M4 Datasheet, PDF (62/68 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
CK#
CK¹
CKE¹
COMMAND⁴
ADDR
DQS
DQ
DM
T0
t_CH
t_IS t_IH
t_IS t_IH
NOP
t_RP²
SELF REFRESH MODE
T1
t_CL
t_IS
Ta0¹
((
))
Ta1
Tb0
((
))
((
((
))
tCK
))
tIS
((
))
((
((
))
))
((
))
AR
((
))
((
))
((
))
((
))
NOP
((
VALID
))
tIS tIH
((
))
VALID
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Enter Self Refresh Mode
((
))
((
))
((
))
((
))
((
))
((
))
tXSNR/
tXSRD3
Exit Self Refresh Mode
DON’T CARE
NOTE: 1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling within
specifications by Ta0.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. ^tXSNR is required before any non-READ command can be applied, and ^tXSRD (200 cycles of CK)
is required before a READ command can be applied.
4. AR = AUTO REFRESH command.
TIMING PARAMETERS
SYMBOL
t_CH
t_CL
t_{CK (2.5)}
t_{CK (2)}
t_IH
-75Z
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
7.5
13
1
-75
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
10
13
1
-8
MIN MAX
0.45 0.55
0.45 0.55
8
13
10
13
1.1
UNITS
t_CK
t_CK
ns
ns
ns
SYMBOL
t_IS
t_RP
t_XSNR
t_XSRD
-75Z
MIN MAX
1
20
75
200
-75
MIN MAX
1
20
75
200
-8
MIN MAX
1.1
20
80
200
UNITS
ns
ns
ns
t_CK
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
62
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©2001, Micron Technology, Inc.