MT46V128M4 Datasheet, PDF (34/68 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
CK#
CK
COMMAND
T0
WRITE
T1 T1n T2 T2n T3
NOP
NOP
NOP
ADDRESS
Bank a,
Col b
t_{DQSS (NOM)}
DQS
t_DQSS
DQ
DI
b
DM
t_{DQSS (MIN)}
DQS
DQ
DM
t_DQSS
DI
b
t_{DQSS (MAX)}
DQS
t_DQSS
DQ
DI
b
DM
T4
NOP
t_WR
T5
T6
PRE⁷
Bank,
(a or all)
NOP
t_RP
NOTE: 1. DI b = data-in for column b.
DON’T CARE
TRANSITIONING DATA
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. ^tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE
commands may be to different devices, in which case ^tWR is not required and the PRECHARGE command could be
applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
Figure 22
WRITE to PRECHARGE – Uninterrupting
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
34
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©2001, Micron Technology, Inc.