MT46V128M4 Datasheet, PDF (24/68 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
CK#
CK
COMMAND
ADDRESS
T0
READ
Bank,
Col n
DQS
T1
BST⁷
CL = 2
T2 T2n T3
T4 T4n T5 T5n
NOP
WRITE
NOP
NOP
Bank,
Col b
tDQSS
(MIN)
DQ
DM
CK#
CK
COMMAND
ADDRESS
T0
READ
Bank a,
Col n
DQS
T1
BST⁷
CL = 2.5
DO
n
T2 T2n T3
NOP
NOP
DI
b
T4
T5 T5n
WRITE
NOP
tDQSS
(MIN)
DQ
DO
DI
n
b
DM
NOTE: 1. DO n = data-out from column n.
DON’T CARE
TRANSITIONING DATA
2. DI b = data-in from column b.
3. Burst length = 4 in the cases shown (applies for bursts of 8 as well; if the burst length is 2,
the BST command shown can be NOP).
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
7. BST = BURST TERMINATE command, page remains open.
Figure 12
READ to WRITE
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
24
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©2001, Micron Technology, Inc.