MT46V128M4 Datasheet, PDF (33/68 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
CK#
CK
COMMAND
T0
WRITE
ADDRESS
Bank a,
Col b
t_{DQSS (NOM)}
DQS
t_DQSS
DQ
DM
T1 T1n T2 T2n T3
NOP
NOP
READ
t_WTR
Bank a,
Col n
DI
b
t_{DQSS (MIN)}
DQS
DQ
DM
t_DQSS
DI
b
t_{DQSS (MAX)}
DQS
t_DQSS
DQ
DI
b
DM
T4
NOP
CL = 2
CL = 2
CL = 2
T5 T5n T6 T6n
NOP
NOP
DI
n
DI
n
DI
n
NOTE: 1. DI b = data-in for column b.
DON’T CARE
TRANSITIONING DATA
2. An interrupted burst of 4 is shown; one data element is written.
3. ^tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM would not be required at T3 -T4n because the READ command would mask the last
four data elements.
Figure 21
WRITE to READ – Odd Number of Data, Interrupting
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
33
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©2001, Micron Technology, Inc.