MT46V128M4 Datasheet, PDF (29/68 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

CK#
CK
COMMAND
T0
WRITE
T1 T1n T2 T2n T3
ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
T4 T4n T5 T5n
NOP
NOP
WRITE
NOP
NOP
ADDRESS
t_{DQSS (NOM)}
DQS
DQ
DM
Bank,
Col b
t_DQSS
DI
b
Bank,
Col n
DI
n
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
FIGURE 17
Nonconsecutive WRITE to WRITE
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
29
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©2001, Micron Technology, Inc.