MT46V16M16CV-6ITK Datasheet, PDF (52/91 Pages) Micron Technology – 256Mb: x4, x8, x16 DDR SDRAM Features

256Mb: x4, x8, x16 DDR SDRAM
Operations
Operations
INITIALIZATION
Prior to normal operation, DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures, other than those specified, may result in
undefined operation.
To ensure device operation, the DRAM must be initialized as described in the following
steps:
1. Simultaneously apply power to V_DD and V_DDQ.
2. Apply V_REF and then V_TT power. V_TT must be applied after V_DDQ to avoid device latch-
up, which may cause permanent damage to the device. Except for CKE, inputs are not
recognized as valid until after V_REF is applied.
3. Assert and hold CKE at a LVCMOS logic LOW. Maintaining an LVCMOS LOW level on
CKE during power-up is required to ensure that the DQ and DQS outputs will be in
the High-Z state, where they will remain until driven in normal operation (by a read
access).
4. Provide stable clock signals.
5. Wait at least 200µs.
6. Bring CKE HIGH, and provide at least one NOP or DESELECT command. At this
point, the CKE input changes from a LVCMOS input to a SSTL_2 input only and will
remain a SSTL_2 input unless a power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least ^tRP time; during this time NOPs or DESELECT commands must be given.
9. Using the LMR command, program the extended mode register (E0 = 0 to enable the
DLL and E1 = 0 for normal drive; or E1 = 1 for reduced drive and E2–En must be set to
0 [where n = most significant bit]).
10. Wait at least ^tMRD time; only NOPs or DESELECT commands are allowed.
11. Using the LMR command, program the mode register to set operating parameters
and to reset the DLL. At least 200 clock cycles are required between a DLL reset and
any READ command.
12. Wait at least ^tMRD time; only NOPs or DESELECT commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least ^tRP time; only NOPs or DESELECT commands are allowed.
15. Issue an AUTO REFRESH command. This may be moved prior to step 13.
16. Wait at least ^tRFC time; only NOPs or DESELECT commands are allowed.
17. Issue an AUTO REFRESH command. This may be moved prior to step 13.
18. Wait at least ^tRFC time; only NOPs or DESELECT commands are allowed.
19. Although not required by the Micron device, JEDEC requires an LMR command to
clear the DLL bit (set M8 = 0). If an LMR command is issued, the same operating
parameters should be utilized as in step 11.
20. Wait at least ^tMRD time; only NOPs or DESELECT commands are supported.
21. At this point the DRAM is ready for any valid command. At least 200 clock cycles with
CKE HIGH are required between step 11 (DLL RESET) and any READ command.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
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