MT46V16M16CV-6ITK Datasheet, PDF (1/91 Pages) Micron Technology – 256Mb: x4, x8, x16 DDR SDRAM Features

256Mb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V64M4 – 16 Meg x 4 x 4 banks
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
Features
• V_DD = 2.5V ±0.2V; V_DDQ = 2.5V ±0.2V
V_DD = 2.6V ±0.1V; V_DDQ = 2.6V ±0.1V (DDR400)¹
• Bidirectional data strobe (DQS) transmitted/
received with data, that is, source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths (BL): 2, 4, or 8
• Auto refresh
– 64ms, 8192-cycle
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2-compatible)
• Concurrent auto precharge option supported
• ^tRAS lockout supported (^tRAP = ^tRCD)
Options
Marking
• Configuration
– 64 Meg x 4 (16 Meg x 4 x 4 banks)
64M4
– 32 Meg x 8 (8 Meg x 8 x 4 banks)
32M8
– 16 Meg x 16 (4 Meg x 16 x 4 banks)
16M16
• Plastic package – OCPL
– 66-pin TSOP
TG
– 66-pin TSOP (Pb-free)
P
• Plastic package
– 60-ball FBGA (8mm x 12.5mm)
CV
– 60-ball FBGA (8mm x 12.5mm)
CY
(Pb-free)
• Timing – cycle time
– 5ns @ CL = 3 (DDR400)
-5B
– 6ns @ CL = 2.5 (DDR333) FBGA only
-6²
– 6ns @ CL = 2.5 (DDR333) TSOP only
-6T²
• Self refresh
– Standard
None
– Low-power self refresh
L
• Temperature rating
– Commercial (0C to +70C)
None
– Industrial (–40C to +85C)
IT
• Revision
– x4, x8, x16
:K⁴
– x4, x8, x16
:M
Notes: 1. DDR400 devices operating at < DDR333
conditions can use V_DD/V_DDQ = 2.5V +0.2V.
2. Available only on Revision K.
3. Available only on Revision M.
4. Not recommended for new designs.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and
CL = 3 (-5B)
Speed Grade
-5B
-6
6T
-75E/-75Z
-75
CL = 2
133
133
133
133
100
Clock Rate (MHz)
CL = 2.5
167
167
167
133
133
CL = 3
200
n/a
n/a
n/a
n/a
Data-Out Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
Access
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ
Skew
0.40ns
0.40ns
0.45ns
0.50ns
0.50ns
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
256Mb_DDR_x4x8x16_D1.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
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Products and specifications discussed herein are subject to change by Micron without notice.