MT46V16M16CV-6ITK Datasheet, PDF (29/91 Pages) Micron Technology – 256Mb: x4, x8, x16 DDR SDRAM Features

256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 13:
Electrical Characteristics and Recommended AC Operating Conditions (-75E)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35;
0°C T_A  70°C; V_DDQ = 2.5V ±0.2V, V_DD = 2.5V ±0.2V
AC Characteristics
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
CL = 2.5
CL = 2
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command to first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising - hold time
DQS falling edge to CK rising - setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command interval
Average periodic refresh interval
AUTO REFRESH command period
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to V_SS
DQS write preamble
DQS write preamble setup time
DQS write postamble
-75E
Symbol
t_AC
t_CH
t_{CK (2.5)}
t_{CK (2)}
t_CL
t_DH
t_DIPW
t_DQSCK
t_DQSH
t_DQSL
t_DQSQ
t_DQSS
t_DS
t_DSH
t_DSS
t_HP
t_HZ
t_IHF
t_IHS
t_IPW
t_ISF
t_ISS
t_LZ
t_MRD
t_QH
t_QHS
t_RAP
t_RAS
t_RC
t_RCD
t_REFC
t_REFI
t_RFC
t_RP
t_RPRE
t_RPST
t_RRD
t_VTD
t_WPRE
t_WPRES
t_WPST
Min
–0.75
0.45
7.5
7.5
0.45
0.5
1.75
–0.75
0.35
0.35
–
0.75
0.5
0.2
0.2
t_CH,
t_CL
–
0.90
1
2.2
0.90
1
–0.75
15
t_{HP -}t_QHS
–
15
40
60
15
–
–
75
15
0.9
0.4
15
0
0.25
0
0.4
Max
0.75
0.55
13
13
0.55
–
–
0.75
–
–
0.5
1.25
–
–
–
–
0.75
–
–
–
–
–
–
–
–
0.75
–
120,000
–
–
70.3
7.8
–
–
1.1
0.6
–
–
–
–
0.6
Units
ns
t_CK
ns
ns
t_CK
ns
ns
ns
t_CK
t_CK
ns
t_CK
ns
t_CK
t_CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
t_CK
t_CK
ns
ns
t_CK
ns
t_CK
Notes
31
46, 52
46, 52
31
27, 32
32
26, 27
27, 32
35
19, 43
15
15
19, 43
26, 27
36, 54
55
24
24
50
44
44
21, 22
20
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.