MT48LC16M4A2_99 Datasheet, PDF (5/55 Pages) Micron Technology – SYNCHRONOUS DRAM

FUNCTIONAL BLOCK DIAGRAM
8 Meg x 8 SDRAM
64Mb: x4, x8, x16
SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
12
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
REFRESH ₁₂
COUNTER
ROW-
12
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 8)
SENSE AMPLIFIERS
4096
2
BANK
CONTROL
LOGIC
2
COLUMN-
ADDRESS
9
9
COUNTER/
LATCH
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
512
(x8)
COLUMN
DECODER
1
1
DATA
8
OUTPUT
REGISTER
8
DATA
8
INPUT
REGISTER
DQM
DQ0-DQ7
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.