MT48LC16M4A2_99 Datasheet, PDF (42/55 Pages) Micron Technology – SYNCHRONOUS DRAM

64Mb: x4, x8, x16
SDRAM
READ – WITH AUTO PRECHARGE ¹
T0
CLK
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
T1
tCK
NOP
DQM /
DQML, DQMH
A0-A9, A11
tAS tAH
ROW
T2
tCL
tCH
READ
tCMS _tCMH
COLUMN m²
T3
NOP
T4
NOP
T5
T6
NOP
NOP
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
DQ
tRCD
tRAS
tRC
ENABLE AUTO PRECHARGE
BANK
tAC
tLZ
CAS Latency
tAC
tOH
DOUT m
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tRP
T7
NOP
tOH
DOUT m + 3
tHZ
T8
ACTIVE
ROW
ROW
BANK
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
t_{AC (3)}
t_{AC (2)}
t_AH
t_AS
t_CH
t_CL
t_{CK (3)}
t_{CK (2)}
t_CKH
t_CKS
-7E
MIN MAX
5.4
5.4
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
-75
MIN MAX
5.4
6
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
-8E
MIN MAX
6
6
1
2
3
3
8
10
1
2
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
t_CMH
t_CMS
t_{HZ (3)}
t_{HZ (2)}
t_LZ
t_OH
t_RAS
t_RC
t_RCD
t_RP
-7E
MIN MAX
0.8
1.5
5.4
5.4
1
2.7
37 120,000
60
15
15
-75
MIN MAX
0.8
1.5
5.4
6
1
2.7
44 120,000
66
20
20
-8E
MIN MAX UNITS
1
ns
2
ns
6
ns
7
ns
1
ns
3
ns
50 120,000 ns
70
ns
20
ns
20
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.