MT48LC16M4A2_99 Datasheet, PDF (29/55 Pages) Micron Technology – SYNCHRONOUS DRAM

64Mb: x4, x8, x16
SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when ^tRC is met. Once
t_{RC is met, the SDRAM will be in the all banks idle state.}
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when ^tMRD has
been met. Once ^tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when ^tRP is met. Once
t_{RP is met, all banks will be in the idle state.}
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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