MT28F322P3 Datasheet, PDF (17/36 Pages) Micron Technology – FLASH MEMORY

Figure 6
BLOCK ERASE Flowchart
Start
Issue ERASE SETUP
Command and
Block Address
Issue BLOCK ERASE
CONFIRM Command
and Block Address
Read Status Register
Bits
NO
SR 7 = 1?
YES
Full Status Register
Check (optional)¹
ERASE
SUSPEND Loop
NO
ERASE
SUSPEND?
YES
BLOCK ERASE
Completed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
SR1 = 0?
YES
NO _{ERASE Attempted}
on a Locked Block
SR3 = 0?
NO
VPP Range Error
YES
SR5 = 0?
NO
BLOCK ERASE Failed
YES
BLOCK ERASE Passed
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
ERASE
SETUP
Data = 20h
Block Addr = Address
within block to be erased
WRITE
ERASE
Data = D0h
Block Addr = Address
within block to be erased
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby
Standby
Standby
Check SR1
1 = Detect locked block
Check SR3²
1 = Detect VPP block
Check SR5³
1 = BLOCK ERASE error
NOTE:
1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
17
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©2002, Micron Technology, Inc.