MT28F322P3 Datasheet, PDF (13/36 Pages) Micron Technology – FLASH MEMORY

(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Figure 6). A two-command erase sequence protects
against accidental erasure of memory contents.
When the BLOCK ERASE CONFIRM command is
complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are cor-
rectly erased. The ERASE operation may be monitored
through the status register (see the Status Register
section).
During the execution of an ERASE operation the
ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
the WSM has reached the suspend state, it allows
the CSM to respond only to the READ ARRAY, READ
STATUS REGISTER, READ QUERY, READ CHIP PRO-
TECTION CONFIGURATION, PROGRAM SETUP, PRO-
GRAM RESUME, ERASE RESUME and LOCK SETUP
(see the Block Locking section). During the ERASE SUS-
PEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
operation, an ERASE RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 7). It is also possible to sus-
pend an ERASE in any bank and initiate a WRITE to
another block in the same bank. After the completion
of a WRITE, an ERASE can be resumed by writing an
ERASE RESUME command.
MODE
Read (array, status registers,
device identification register, or
query)
Standby
Output Disable
Reset
Write
Table 6
Bus Operations
RST#
VIH
CE#
VIL
OE#
VIL
VIH
VIH
X
VIH
VIH
X
VIL
X
X
VIH
VIL
VIH
WE#
VIH
ADDRESS DQ0–DQ15
X
DOUT
X
X
High-Z
X
X
High-Z
X
X
High-Z
VIL
X
DIN
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
13
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©2002, Micron Technology, Inc.