MRF24J40_10 Datasheet, PDF (91/156 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.3 Interrupts
The MRF24J40 has one interrupt (INT) pin 16 that
signals one of eight interrupt events to the host
microcontroller. The interrupt structure is shown in
Figure 3-1. Interrupts are enabled via the INTCON
(0x32) register. Interrupt flags are located in the
INTSTAT (0x31) register. The INTSTAT register
clears-to-zero upon read. Therefore, the host
microcontroller should read and store the INTSTAT
register and check the bits to determine which interrupt
occurred. The INT pin will continue to signal an
FIGURE 3-1:
MRF24J40 INTERRUPT LOGIC
interrupt until the INTSTAT register is read. The edge
polarity of the INT pin is configured via the INTEDGE
bit in the SLPCON0 (0x211<1>) register.
Note 1: The INTEDGE polarity defaults to:
0 = Falling Edge. Ensure that the inter-
rupt polarity matches the interrupt pin
polarity of the host microcontroller.
2: The INT pin will remain high or low,
depending on INTEDGE polarity setting,
until INTSTAT register is read.
INTSTAT.SLPIF
INTCON.SLPIE
INTSTAT.WAKEIF
INTCON.WAKEIE
INTSTAT.HSYMTMRIF
INTCON.HSYMTMRIE
SLPCON0.INTEDGE
INTSTAT.SECIF
INTCON.SECIE
INT
INTSTAT.RXIF
INTCON.RXIE
INTSTAT.TXG2IF
INTCON.TXG2IE
INTSTAT.TXG1IF
INTCON.TXG1IE
INTSTAT.TXNIF
INTCON.TXNIE
TABLE 3-3: REGISTERS ASSOCIATED WITH INTERRUPTS
Addr. Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
0x31 INTSTAT
0x32 INTCON
0x211 SLPCON0
SLPIF
SLPIE
r
WAKEIF HSYMTMRIF
WAKEIE HSYMTMRIE
r
r
SECIF
SECIE
r
RXIF
RXIE
r
Bit 2
TXG2IF
TXG2IE
r
Bit 1
TXG1IF
TXG1IE
INTEDGE
Bit 0
TXNIF
TXNIE
SLPCKEN
© 2010 Microchip Technology Inc.
Preliminary
DS39776C-page 91