MRF24J40_10 Datasheet, PDF (73/156 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-78: MAINCNT0: MAIN COUNTER 0 REGISTER (ADDRESS: 0x226)
R/W-0
MAINCNT7
bit 7
R/W-0
MAINCNT6
R/W-0
MAINCNT5
R/W-0
MAINCNT4
R/W-0
MAINCNT3
R/W-0
MAINCNT2
R/W-0
MAINCNT1
R/W-0
MAINCNT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MAINCNT<7:0>: Main Counter bits
Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI)
and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices.
Units: SLPCLK.⁽¹⁾
Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and
Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
REGISTER 2-79: MAINCNT1: MAIN COUNTER 1 REGISTER (ADDRESS: 0x227)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MAINCNT15 MAINCNT14 MAINCNT13 MAINCNT12 MAINCNT11 MAINCNT10
bit 7
R/W-0
MAINCNT9
R/W-0
MAINCNT8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MAINCNT<15:8>: Main Counter bits
Main counter is a 26-bit counter. Together with the remain counter times events: Beacon Interval (BI)
and inactive period for beacon-enabled devices and Sleep interval for nonbeacon-enabled devices.
Units: SLPCLK.⁽¹⁾
Note 1: Sleep Clock (SLPCLK) period depends on the Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> and
Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
© 2010 Microchip Technology Inc.
Preliminary
DS39776C-page 73