MRF24J40_10 Datasheet, PDF (19/156 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
TABLE 2-6: SHORT ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40 (CONTINUED)
Addr. File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Details
on
Page:
0x30 RXSR
r
UPSECERR
BATIND
r
r
SECDECERR
r
r
0000
52
0000
0x31 INTSTAT
SLPIF
WAKEIF
HSYMTMRIF
SECIF
RXIF
TXG2IF
TXG1IF
TXNIF
0000
53
0000
0x32 INTCON
SLPIE
WAKEIE
HSYMTMRIE
SECIE
RXIE
TXG2IE
TXG1IE
TXNIE
1111
54
1111
0x33 GPIO
r
r
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
0000
55
0000
0x34 TRISGPIO
r
r
TRISGP5
TRISGP4
TRISGP3
TRISGP2
TRISGP1
TRISGP0
0000
55
0000
0x35 SLPACK
SLPACK
WAKECNT6 WAKECNT5
WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0
0000
56
0000
0x36 RFCTL
r
r
r
WAKECNT8 WAKECNT7
RFRST
RFTXMODE RFRXMODE 0000
57
0000
0x37 SECCR2
UPDEC
UPENC
TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0 0000
58
0000
0x38 BBREG0
r
r
r
r
r
r
r
TURBO
0000
59
0000
0x39 BBREG1
r
r
r
r
r
RXDECINV
r
r
0000
59
0000
0x3A BBREG2
CCAMODE1 CCAMODE0 CCACSTH3
CCACSTH2 CCACSTH1 CCACSTH0
r
r
0100
60
1000
0x3B BBREG3 PREVALIDTH3 PREVALIDTH2 PREVALIDTH1 PREVALIDTH0 PREDETTH2 PREDETTH1 PREDETTH0
r
1101
60
1000
0x3C BBREG4
CSTH2
CSTH1
CSTH0
PRECNT2
PRECNT1
PRECNT0
r
r
1001
61
1100
0x3D Reserved
r
r
r
r
r
r
r
r
0000
—
0000
0x3E BBREG6
RSSIMODE1 RSSIMODE2
r
r
r
r
r
RSSIRDY
0000
61
0001
0x3F CCAEDTH CCAEDTH7 CCAEDTH6
CCAEDTH5
CCAEDTH4
CCAEDTH3 CCAEDTH2 CCAEDTH1 CCAEDTH0
0000
62
0000
Legend:
r = reserved
TABLE 2-7: LONG ADDRESS CONTROL REGISTER SUMMARY FOR MRF24J40
Addr. File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Details
on
Page:
0x200 RFCON0
CHANNEL3
0x201 RFCON1
VCOOPT7
0x202 RFCON2
PLLEN
0x203 RFCON3
TXPWRL1
0x204 Reserved
r
0x205 RFCON5
BATTH3
0x206 RFCON6
TXFIL
0x207 RFCON7
SLPCLKSEL1
0x208 RFCON8
r
0x209 SLPCAL0
SLPCAL7
0x20A SLPCAL1
SLPCAL15
0x20B SLPCAL2
SLPCALRDY
0x20C Reserved
r
0x20D Reserved
r
0x20E Reserved
r
0x20F RFSTATE
RFSTATE2
0x210 RSSI
RSSI7
0x211 SLPCON0
r
0x212 Reserved
r
Legend:
r = reserved
CHANNEL2
VCOOPT6
r
TXPWRL0
r
BATTH2
r
SLPCLKSEL0
r
SLPCAL6
SLPCAL14
r
r
r
r
RFSTATE1
RSSI6
r
r
CHANNEL1
VCOOPT5
r
TXPWRS2
r
BATTH1
r
r
r
SLPCAL5
SLPCAL13
r
r
r
r
RFSTATE0
RSSI5
r
r
CHANNEL0
VCOOPT4
r
TXPWRS1
r
BATTH0
20MRECVR
r
RFVCO
SLPCAL4
SLPCAL12
SLPCALEN
r
r
r
r
RSSI4
r
r
RFOPT3
VCOOPT3
r
TXPWRS0
r
r
BATEN
r
r
SLPCAL3
SLPCAL11
SLPCAL19
r
r
r
r
RSSI3
r
r
RFOPT2
VCOOPT2
r
r
r
r
r
r
r
SLPCAL2
SLPCAL10
SLPCAL18
r
r
r
r
RSSI2
r
r
RFOPT1
RFOPT0 0000 0000 63
VCOOPT1
VCOOPT0 0000 0000 63
r
r
0000 0000 64
r
r
0000 0000 64
r
r
0000 0000 —
r
r
0000 0000 65
r
r
0000 0000 65
CLKOUTMODE1 CLKOUTMODE0 0000 0000 66
r
r
0000 0000 66
SLPCAL1
SLPCAL0 0000 0000 67
SLPCAL9
SLPCAL8 0000 0000 67
SLPCAL17
SLPCAL16 0000 0000 68
r
r
0000 0000 —
r
r
0000 0000 —
r
r
0000 0000 —
r
r
0000 0000 69
RSSI1
RSSI0
0000 0000 69
INTEDGE
SLPCLKEN 0000 0000 70
r
r
0000 0000 —
© 2010 Microchip Technology Inc.
Preliminary
DS39776C-page 19