MRF24J40_10 Datasheet, PDF (90/156 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.2 Initialization
Certain control register values must be initialized for
basic operations. These values differ from the
Power-on Reset values and provide improved opera-
tional parameters. These settings are normally made
once after a Reset. After initialization, MRF24J40
features can be configured for the application. The
steps for initialization are shown in Example 3-1.
EXAMPLE 3-1: INITIALIZING THE MRF24J40
Example steps to initialize the MRF24J40:
1. SOFTRST (0x2A) = 0x07 – Perform a software Reset. The bits will be automatically cleared to ‘0’ by hardware.
2. PACON2 (0x18) = 0x98 – Initialize FIFOEN = 1 and TXONTS = 0x6.
3. TXSTBL (0x2E) = 0x95 – Initialize RFSTBL = 0x9.
4. RFCON0 (0x200) = 0x03 – Initialize RFOPT = 0x03.
5. RFCON1 (0x201) = 0x01 – Initialize VCOOPT = 0x02.
6. RFCON2 (0x202) = 0x80 – Enable PLL (PLLEN = 1).
7. RFCON6 (0x206) = 0x90 – Initialize TXFIL = 1 and 20MRECVR = 1.
8. RFCON7 (0x207) = 0x80 – Initialize SLPCLKSEL = 0x2 (100 kHz Internal oscillator).
9. RFCON8 (0x208) = 0x10 – Initialize RFVCO = 1.
10. SLPCON1 (0x220) = 0x21 – Initialize CLKOUTEN = 1 and SLPCLKDIV = 0x01.
Configuration for nonbeacon-enabled devices (see Section 3.8 “Beacon-Enabled and Nonbeacon-Enabled
Networks”):
11. BBREG2 (0x3A) = 0x80 – Set CCA mode to ED.
12. CCAEDTH = 0x60 – Set CCA ED threshold.
13. BBREG6 (0x3E) = 0x40 – Set appended RSSI value to RXFIFO.
14. Enable interrupts – See Section 3.3 “Interrupts”.
15. Set channel – See Section 3.4 “Channel Selection”.
Note: Maintain 0x200<3:0> = 0x03
16. Set transmitter power - See “REGISTER 2-62: RF CONTROL 3 REGISTER (ADDRESS: 0x203)”.
17. RFCTL (0x36) = 0x04 – Reset RF state machine.
18. RFCTL (0x36) = 0x00.
19. Delay at least 192 μs.
TABLE 3-2: REGISTERS ASSOCIATED WITH INITIALIZATION
Addr. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x18 PACON2 FIFOEN
r
TXONTS3 TXONTS2 TXONTS1 TXONTS0 TXONT8 TXONT7
0x2A SOFTRST
r
r
r
r
r
RSTPWR
RSTBB
RSTMAC
0x2E TXSTBL RFSTBL3 RFSTBL2 RFSTBL1 RFSTBL0 MSIFS3
MSIFS2
MSIFS1
MSIFS0
0x201 RFCON1 VCOOPT7 VCOOPT6 VCOOPT5 VCOOPT4 VCOOPT3 VCOOPT2 VCOOPT1 VCOOPT0
0x202 RFCON2
PLLEN
r
r
r
r
r
r
r
0x206 RFCON6
TXFIL
r
r
20MRECVR BATEN
r
r
r
0x207 RFCON7 SLPCLKSEL1 SLPSCKSEL0
r
r
r
r
r
r
0x208 RFCON8
r
r
r
RFVCO
r
r
r
r
0x220 SLPCON1
r
r
CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0
DS39776C-page 90
Preliminary
© 2010 Microchip Technology Inc.