EQCO30R5.D Datasheet, PDF (9/24 Pages) Microchip Technology – EQCO30R5.D 3G/HD-SDI Video Cable Equalizer

EQCO30R5.D
2.1.2 GUIDELINES FOR PCB LAYOUT
All components in the high-speed signal path should be
0402 size for minimal parasitic effects.
The transmission line between the BNC connector and
the return-loss network (L1, R2) shall be a 75Ω single-
ended transmission line. Components R2, R4 and R5
are 75Ω resistors, and component L1 is a 2.7 nH
inductor. Component R3 is the 75Ω termination resistor
to GND. Components C1 and C2 are AC coupling
capacitors connected to the input of the chip. Two
decoupling capacitors (C10, C11) are placed between
VCC and GND, close to the chip. The output of the chip
is connected to the deserializer or FPGA with a 100Ω
differential transmission line. To minimize unwanted
parasitic effects, a cutout of the ground and power
plane is made underneath capacitor C6 and
underneath the input pins of the EQCO30R5 chip.
Figure 2-2 shows a recommended layout for the
EQCO30R5 implementation.
FIGURE 2-2:
RECOMMENDED PCB LAYOUT FOR EQCO30R5
 2011-2016 Microchip Technology Inc.
DS60001304B-page 9