EQCO30R5.D Datasheet, PDF (6/24 Pages) Microchip Technology – EQCO30R5.D 3G/HD-SDI Video Cable Equalizer

EQCO30R5.D
1.1.1 SDIp/SDIn
SDIp/SDIn together form a differential input pair. The
EQCO30R5 analyzes the differential voltage between
these pins and adaptively equalizes for signal level and
frequency response. The equalizer automatically
detects and adapts to signals with different edge rates,
different attenuation levels and different cable
characteristics. Both SDIp and SDIn inputs need to be
terminated by an external 75Ω resistor to GND.
1.1.2 SDOp/SDOn
SDOp/SDOn together form a differential CML pair
outputting the reconstructed far-end transmit signal.
SDOp/SDOn are terminated on-chip with two 50Ω
resistors to 1.2V. These outputs should be AC coupled
to the deserializer (unless a 800 mV-1V common-mode
voltage is acceptable). For SMPTE signals, it is best to
use 4.7 µF AC coupling capacitors.
1.1.3 LFI
LFI is the uplink input signal that will be transmitted on
the SDIp/SDIn pair. LFI must be a 0-1.2V signal. The
pin has an internal resistor of 3.6 kΩ. When driving with
a 3.3V (2.5V) signal, an external resistor of 6.2 kΩ (3.9
kΩ) should be placed in series close to the EQCO30R5
chip. When not using uplink communications, leave this
pin floating.
1.1.4 AmpR
AmpR is a VCC resistor that sets the transmit ampli-
tude of the uplink output driver. The typical value is
R_amp = 1 kΩ for 150 mV transmit amplitude. When not
using uplink communications, leave this pin floating.
DS60001304B-page 6
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