EQCO30R5.D Datasheet, PDF (7/24 Pages) Microchip Technology – EQCO30R5.D 3G/HD-SDI Video Cable Equalizer

EQCO30R5.D
1.2 Circuit Operation
FIGURE 1-3:
EQCO30R5.D BLOCK DIAGRAM SHOWING ELECTRICAL CONNECTIONS
LFI, AmpR
SDIp
SDIn
Equalizer
Core
Limiting Amplifier
with DC restore
+ CML Driver
SDOp
SDOn
EQCO30R5
1.2.1 EQUALIZER CORE
The EQCO30R5 has an embedded equalizer in the
receive path with the following characteristics:
• Auto-Adaptive
The equalizer controls a multiple-pole analog filter
which compensates for attenuation of the cable, as
illustrated in Figure 1-4. The filter frequency response
needed to restore the signal is automatically determined
by the device using a time-continuous feedback loop
that measures the frequency components in the signal.
Upon the detection of a valid signal, the control loop
converges within a few microseconds.
• Variable Gain
The EQCO30R5 equalizer has variable gain to
compensate for low-frequency attenuation through the
coax and variations in transmit amplitude; this makes
the equalizer performance more robust, even at
maximum cable lengths.
• Variable Coax
The equalizer can receive attenuated signals from
other types of cables besides the Belden1694A.
• Multi-Speed
The EQCO30R5 works at data rates from 143 Mbps to
2.97 Gbps. With 8B/10B coding, the allowable bit rate
is extended from 50 Mbps to 3.125 Gbps.
Example equalizer performance measurements can be
found in Appendix B: “Typical Equalizer
Characteristics”.
1.2.2 RX OUTPUT DRIVER
The output driver converts the output of the equalizer
core to an LVDS-like signal and sends it onto a 100Ω
differential transmission line.
FIGURE 1-4:
PRINCIPLE OF EQUALIZER OPERATION
 2011-2016 Microchip Technology Inc.
DS60001304B-page 7