KSZ8081MNX Datasheet, PDF (8/66 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

KSZ8081MNX/RNB
TABLE 2-1:
Pin
Number
31
PIN DESCRIPTION — KSZ8081MNX (CONTINUED)
Name
LED1/
SPEED
Buffer
Type
(Note 2-1)
Description
Ipu/O
LED Output: Programmable LED1 Output.
Config Mode: Latched as Speed (Register 0h, Bit [13]) at the de-
assertion of reset.
See the Strap-In Options – KSZ8081MNX section for details.
The LED1 pin is programmable using Register 1Fh bits [5:4], and is
defined as follows:
:
LED Mode = [00]
Speed
Pin State
10Base-T
High
100Base-TX
Low
LED Definition
OFF
ON
32
PADDLE
Note 2-1
Note 2-2
Note 2-3
Note 2-4
LED Mode = [01]
Activity
Pin State
No activity
High
Activity
Toggle
LED Mode = [10], [11]Reserved
LED Definition
OFF
Blinking
RST#
Ipu
Chip Reset (active low).
GND
GND
Ground.
P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
NC = Pin is not bonded to the die.
RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0]
presents valid data from the MAC. TXD[3:0] has no effect on the PHY when TXEN is de-asserted.
DS00002202A-page 8
 2016 Microchip Technology Inc.