KSZ8081MNX Datasheet, PDF (10/66 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

KSZ8081MNX/RNB
FIGURE 2-2:
KSZ8081RNB 32-QFN PIN ASSIGNMENT (TOP VIEW)
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
XO
32 31 30 29 28 27 26 25
1
24
2
23
3
22
PADDLE
4
GROUND
21
5
(ON BOTTOM OF CHIP) 20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
TXD0
TXEN
NC
INTRP/NAND_TREE#
RXER/ISO
REF_CLK/B-CAST_OFF
CRS_DV/CONFIG2
VDDIO
TABLE 2-3: PIN DESCRIPTION — KSZ8081RNB
Pin Number
Pin Name
Type (Note 2-1)
Pin Function
1
GND
GND
Ground
2
VDD_1.2
P
1.2V core V_DD (power supplied by KSZ8081RNB)_.
Decouple with 2.2 μF and 0.1 μF capacitors to ground.
3
VDDA_3.3
4
RXM
P
3.3V analog V_DD.
I/O
Physical receive or transmit signal ( differential).
5
RXP
I/O
Physical receive or transmit signal (+ differential).
6
TXM
I/O
Physical transmit or receive signal ( differential).
7
TXP
I/O
Physical transmit or receive signal (+ differential).
8
XO
O
Crystal feedback for 25 MHz crystal. This pin is a no con-
nect if an oscillator or external clock source is used.
9
XI
25 MHz Mode: 25 MHz ±50 ppm Crystal / Oscillator /
I
External Clock Input
50 MHz Mode: 50 MHz ±50 ppm Oscillator / External
Clock Input
10
REXT
I
Set PHY transmit output current. Connect a 6.49 kΩ
resistor to ground on this pin.
Management Interface (MII) Data I/O. This pin has a
11
MDIO
Ipu/Opu
weak pull-up, is open-drain, and requires an external
1.0 kΩ pull-up resistor.
12
MDC
Ipu
Management Interface (MII) Clock Input. This clock pin is
synchronous to the MDIO data pin.
The pull-up/pull-down value is latched as PHYADDR[0] at
13
PHYAD0
Ipu/O
the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
DS00002202A-page 10
 2016 Microchip Technology Inc.