TC1054 Datasheet, PDF (7/18 Pages) TelCom Semiconductor, Inc – 50mA CMOS LDO WITH SHUTDOWN AND ERROR OUTPUT

TC1054/TC1055/TC1186
4.0 THERMAL CONSIDERATIONS
4.1 Thermal Shutdown
Integrated thermal protection circuitry shuts the
regulator off when die temperature exceeds 160°C.
The regulator remains off until the die temperature
drops to approximately 150°C.
4.2 Power Dissipation
The amount of power the regulator dissipates is
primarily a function of input and output voltage, and
output current. The following equation is used to
calculate worst case actual power dissipation:
EQUATION 4-1:
P_D ≈ (V_INMAX – V_OUTMIN)I_LOADMAX
Where:
P_D = Worst case actual power dissipation
V_INMAX = Maximum voltage on V_IN
V_OUTMIN = Minimum regulator output voltage
I_LOADMAX = Maximum output (load) current
The maximum allowable power dissipation
(Equation 4-2) is a function of the maximum ambient
temperature (T_AMAX), the maximum allowable die
temperature (T_JMAX) and the thermal resistance from
junction-to-air (θ_JA). The 5-Pin SOT-23A package has
a θ_JA of approximately 220°C/Watt.
EQUATION 4-2:
P_DMAX= (T_JMAX – T_AMAX)
θ_JA
Where all terms are previously defined.
Equation 4-1 can be used in conjunction with
Equation 4-2 to ensure regulator thermal operation is
within limits. For example:
Given:
V_INMAX = 3.0V ±5%
V_OUTMIN = 2.7V – 2.5%
I_LOADMAX = 40mA
T_JMAX = 125°C
T_AMAX = 55°C
Find: 1. Actual power dissipation
2. Maximum allowable dissipation
Actual power dissipation:
PD ≈ (V_INMAX – V_OUTMIN)I_LOADMAX
= [(3.0 x 1.05) – (2.7 x .975)]40 x 10^–3
= 20.7mW
Maximum allowable power dissipation:
P_DMAX = (T_JMAX – T_AMAX)
θ_JA
= (125 – 55)
220
= 318mW
In this example, the TC1054 dissipates a maximum of
20.7mW; below the allowable limit of 318mW. In a
similar manner, Equation 4-1 and Equation 4-2 can be
used to calculate maximum current and/or input
voltage limits.
4.3 Layout Considerations
The primary path of heat conduction out of the package
is via the package leads. Therefore, layouts having a
ground plane, wide traces at the pads, and wide power
supply bus lines combine to lower θ_JA and therefore,
increase the maximum allowable power dissipation
limit.
© 2002 Microchip Technology Inc.
DS21350B-page 7