PIC18F46K80-E-PT Datasheet, PDF (7/12 Pages) Microchip Technology – PIC18F66K80 Family Silicon Errata and Data Sheet Clarification

9. Module: MCLRE
The Master Clear pin will not be readable when
MCLRE is set to off for all 28-pin part variants
(PIC18F2XK80). When the MCLRE bit,
CONFIG3H<7>, is cleared on 28-pin devices,
the MCLR pin will be disabled but input data will
not be available on RE3.
Work around
None.
Affected Silicon Revisions
A2 A3 A4
XXX
PIC18F66K80
10. Module: Timer1/Timer3
Timer1 and Timer3 gate control will not function
up to the speed of FOSC when the TxCON is set
to the system clock (TxCON<7:6> = 01). Results
will always be at the resolution of FOSC/4,
although the internal FOSC has been selected as
the clock source.
Work around
Use the external clock input pin setting,
TxCON<7:6> = 10 and TxCON<3> = 0.
Affected Silicon Revisions
A2 A3 A4
XX
 2011 Microchip Technology Inc.
DS80519D-page 7