PIC18F46K80-E-PT Datasheet, PDF (2/12 Pages) Microchip Technology – PIC18F66K80 Family Silicon Errata and Data Sheet Clarification

PIC18F66K80
TABLE 2: SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Issue Summary
Affected Revisions⁽¹⁾
A2
A3
A4
Analog-to-Digital A/D
Converter (A/D) Performance
1. The 12-bit A/D performance is outside of
X
X
X
data sheet’s A/D Converter specifications.
EUSART
Synchronous
Transmit
2. When using the Synchronous Transmit
X
mode, transmitted data may become cor-
rupted if using the TXxIF bit to determine
when to load the TXREGx register.
ECCP
Auto-Shutdown
3. The tri-state setting of the auto-shutdown
X
X
X
feature in the enhanced PWM will not
successfully drive the pin to tri-state.
ECAN
CAN Clock
4. CLKSEL bit in the CIOCON register is
X
Source Selection
modifiable while the ECAN module is
active.
Ultra Low-Power Sleep Entry
Sleep
5. Entering Ultra Low-Power Sleep mode by X
setting RETEN = 0 and SRETEN = 1, will
cause the part to not be programmable
through ICSP™.
IPD and IDD
Maximum Limit
6. Maximum current limits may be higher
X
than specified in Table 31-2 of the data
sheet.
Reset (BOR) Enable/Disable
An unexpected Reset may occur if the
Brown-out Reset module (BOR) is dis-
7.
abled, and then re-enabled, when the
High/Low-Voltage Detection module
(HLVD) is not enabled
(HLVDCON<4> = 0).
X
X
X
ECAN
EWIN
8. The enhanced window address feature,
X
EWIN<4:0>, in the ECANCON register, will
not move the BnCON 0<n<5 registers into
the access window of RAM.
MCLRE
Master Clear
Enable
9. The Master Clear pin will not be readable X
X
X
when MCLRE is set to off for all 28-pin part
variants (PIC18F2XK80).
Timer1/
Timer3
Gated Enable
10. Timer1 and Timer3 gate control will not
X
X
function up to the speed of FOSC when the
TxCON is set to the system clock
(TxCON<7:6> = 01).
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
DS80519D-page 2
 2011 Microchip Technology Inc.