PIC18F46K80-E-PT Datasheet, PDF (4/12 Pages) Microchip Technology – PIC18F66K80 Family Silicon Errata and Data Sheet Clarification

PIC18F66K80
2. Module: EUSART
In Synchronous Transmit mode, data may be cor-
rupted if using the TXxIF bit to determine when to
load the TXREGx register. One or more of the
intended transmit messages may be incorrect.
Work around
A fixed delay added before loading the TXREGx
may not be a reliable work around. When load-
ing the TXREGx, check that the TRMT bit inside
of the TXSTAx register is set instead of checking
the TXxIF bit. The following code can be used:
while(!TXSTAxbits.TRMT);
// wait to load TXREGx until TRMT is set
Affected Silicon Revisions
A2 A3 A4
X
3. Module: ECCP
The tri-state setting of the auto-shutdown
feature, in the enhanced PWM, will not success-
fully drive the pin to tri-state. The pin will remain
an output and should not be driven externally. All
tri-state settings will be affected.
Work around
Use one of the other two auto-shutdown states
available, as outlined in the data sheet.
Affected Silicon Revisions
A2 A3 A4
XXX
4. Module: ECAN
The CLKSEL bit in the CIOCON register remains
modifiable while the ECAN module is not in Con-
figuration mode. Accidental state changes of this
bit will result in immediate bit clock changes that
will affect all nodes on the bus.
Work around
While the ECAN module is in Run mode, do not
modify the state of the CLKSEL bit in the
CIOCON register unless the CAN module is first
changed into Configuration mode.
Affected Silicon Revisions
A2 A3 A4
X
5. Module: Ultra Low-Power Sleep
Entering Ultra Low-Power Sleep mode by setting
RETEN = 0 and SRETEN = 1, will cause the part
to not be programmable through ICSP. This issue
occurs when the RETEN fuse bit in
CONFIG1L<0> is cleared to ‘0’, the SRETEN bit
in the WDTCON register is set to ‘1’ and a SLEEP
instruction is executed within the first 350 s of
code execution. This happens after a Reset
event, causing the part to enter Ultra Low-Power
Sleep mode.
Work around
Use normal Sleep and Low-Power Sleep modes
only, or on any Reset, ensure that at least
350 s passes before executing a SLEEP
instruction when ULP is enabled. To ensure the
Ultra Low-Power Sleep mode is not enabled, the
RETEN fuse bit in CONFIG1L<0> should be set
to a ‘1’, and the SRETEN bit in the WDTCON
register should be cleared to a ‘0’. The following
code can be used:
//This will ensure the RETEN fuse is set to 1
#pragma config RETEN = OFF
//This will ensure the SRETEN bit is 0
WDTCONbits.SRETEN = 0;
If the Ultra Low-Power Sleep mode is needed,
then the user must ensure that the minimum
time, before the first SLEEP instruction is
executed, is greater than 350 s.
Affected Silicon Revisions
A2 A3 A4
X
DS80519D-page 4
 2011 Microchip Technology Inc.