PIC18F46K80-E-PT Datasheet, PDF (3/12 Pages) Microchip Technology – PIC18F66K80 Family Silicon Errata and Data Sheet Clarification

PIC18F66K80
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
1. Module: Analog-to-Digital Converter (A/D)
The 12-bit A/D performance is outside of the
data sheet’s A/D Converter specifications.
When used as a 12-bit A/D, the possible issues
are high offset error, up to a maximum of
±25 LSBs; high DNL error, up to a maximum of
+6.0/-4.0 LSBs; and multiple missing codes, up
to a maximum of twenty. Users should evaluate
the 12-bit A/D performance in their application
using the suggested work around below. See
Table 3 for guidance specifications.
The 12-bit A/D issues will be fixed in future
revisions of this part. Reduced bit resolution
specifications can be derived by dividing, as
appropriate. For instance, 10-bit guidance is
obtained by dividing the parameters in Table 3
by four.
A/D Offset
The A/D may have high offset error, up to a
maximum of ±25 LSBs; it can be used if the A/D
is calibrated for the offset.
Work around
Calibrate for offset in Single-Ended mode by
connecting A/D +ve input to ground and taking
the A/D reading. This will be the offset of the
device and can be used to compensate for the
subsequent A/D readings on the actual inputs.
TABLE 3: A/D CONVERTER CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ
Max Units
Conditions
A01 NR Resolution
—
—
12
bit VREF  5.0V
A03 EIL Integral Linearity Error
—
—
±10.0
LSb VREF  5.0V
A04 EDL Differential Linearity Error
—
—
+6.0/-4.0 LSb VREF  5.0V
A06 EOFF Offset Error
—
—
±25
LSb VREF  5.0V
A07 EGN Gain Error
A10 —
Monotonicity⁽¹⁾
—
—
±15
LSb VREF  5.0V
—
VSS  VAIN VREF
A20 VREF Reference Voltage Range
(VREFH – VREFL)
3
— AVDD – AVSS V
A21 VREFH Reference Voltage High
AVSS + 3.0V — AVDD + 0.3V V
A22 VREFL Reference Voltage Low
AVSS – 0.3V — AVDD – 3.0V V
A25 VAIN Analog Input Voltage
VREFL
—
VREFH
V
Note 1: The A/D conversion result never decreases with an increase in the input voltage.
Affected Silicon Revisions
A2 A3 A4
XXX
 2011 Microchip Technology Inc.
DS80519D-page 3