MRF24J40MB-I Datasheet, PDF (68/156 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
REGISTER 2-69: SLPCAL2: SLEEP CALIBRATION 2 REGISTER (ADDRESS: 0x20B)
R-0
SLPCALRDY
bit 7
R/W-0
r
R/W-0
r
W-0
R-0
SLPCALEN SLPCAL19
R-0
SLPCAL18
R-0
SLPCAL17
R-0
SLPCAL16
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-5
bit 4
bit 3-0
SLPCALRDY: Sleep Calibration Ready bit
1 = Sleep calibration count is complete
Reserved: Maintain as ‘0’
SLPCALEN: Sleep Calibration Enable bit
1 = Starts the Sleep calibration counter. Automatically cleared to ‘0’ by hardware
SLPCAL<19:16>: Sleep Calibration Counter bits
20-bit counter to calibrate the Sleep Clock (SLPCLK) period. The counter contains the count of
16 SLPCLK periods. The SLPCLK period depends on the Sleep Clock Selection (SLPCLKSEL),
RFCON7<7:6> and Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick (50 ns).
DS39776C-page 68
Preliminary
© 2010 Microchip Technology Inc.