MRF24J40MB-I Datasheet, PDF (128/156 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
3.17 Security
The MRF24J40 provides a hardware security engine
that implements the Advanced Encryption Standard,
128-bit (AES-128) according to the IEEE 802.15.4-2003
Standard. The MRF24J40 supports seven security
suites which provide a group of security operations
designed to provide security services on MAC and upper
layer frames.
• AES-CTR
• AES-CCM-128
• AES-CCM-64
• AES-CCM-32
• AES-CRC-MAC-128
• AES-CRC-MAC-64
• AES-CRC-MAC-32
Security keys are stored in the Security Key FIFO. Four
security keys, three for encryption and one for decryption,
are stored in the memory locations shown in Figure 3-20.
The security engine can be used for the encryption and
decryption of MAC sublayer frames for transmission
and reception of secured frames and provide security
encryption and decryption services to the upper layers.
These functions are described in the following
subsections.
3.17.1 MAC SUBLAYER TRANSMIT
ENCRYPTION
A frame can be encrypted and transmitted from each of
the TX FIFOs. Table 3-23 lists the TX FIFO and associ-
ated security key memory address and control register
bits.
FIGURE 3-20:
MEMORY MAP OF
SECURITY KEY FIFO
Long Address
Memory Space
0x280
0x28F
0x290
0x29F
0x2A0
0x2AF
0x2B0
0x2BF
TX Normal FIFO
Security Key
TX GTS1 FIFO
Security Key
TX GTS2 FIFO/
TX Beacon FIFO
Security Key
RX FIFO
Security Key
16 bytes
16 bytes
16 bytes
16 bytes
Note:
The TX GTS2 FIFO and TX Beacon FIFO
share the same security key memory
location.
TABLE 3-23: ENCRYPTION SECURITY KEY AND CONTROL REGISTER BITS
TX FIFO
Security Key
Memory Address
Security Suite
Select Bits
Security Enable Bits
Trigger Bit
TX Normal FIFO
0x280-0x28F
TXNCIPHER
TXNSECEN
TXNTRIG
(SECCON0 0x2C<2:0>) (TXNCON 0x1B<1>) (TXNCON 0x1B<0>)
TX GTS1 FIFO
0x290-0x29F
TXG1CIPHER
TXG1SECEN
TXG1TRIG
(SECCR2 0x37<2:0>) (TXG1CON 0x1C<1>) (TXG1CON 0x1C<0>)
TX GTS2 FIFO
0x2A0-0x2AF
TXG2CIPHER
TXG2SECEN
TXG2TRIG
(SECCR2 0x37<5:3>) (TXG2CON 0x1D<1>) (TXG2CON 0x1D<0>)
TX Beacon FIFO
0x2A0-0x2AF
TXBCIPHER
TXBCNSECEN
TXBCNTRIG
(SECCON1 0x2D<6:4>) (TXBCON 0x1A<1>) (TXBCON 0x1A<0>)
Note: The TX GTS2 FIFO and TX Beacon FIFO share the same security key memory location.
DS39776C-page 128
Preliminary
© 2010 Microchip Technology Inc.