MRF24J40MB-I Datasheet, PDF (13/156 Pages) Microchip Technology – IEEE 802.15.4™ 2.4 GHz RF Transceiver

MRF24J40
2.14 Memory Organization
Memory in the MRF24J40 is implemented as static
RAM and is accessible via the SPI port. Memory is
functionally divided into control registers and data buf-
fers (FIFOs), as shown in Figure 2-6. Control registers
provide control, status and device addressing for
MRF24J40 operations. FIFOs serve as temporary
buffers for data transmission, reception and security
keys. Memory is accessed via two addressing
methods: Short and Long.
FIGURE 2-6:
MEMORY MAP FOR MRF24J40
0x00
0x3F
Short Address
Memory Space
Control Registers
64 bytes
Long Address
Memory Space
0x000
TX Normal FIFO
0x07F
0x080
TX Beacon FIFO
0x0FF
0x100
TX GTS1 FIFO
0x17F
0x180
TX GTS2 FIFO
0x1FF
0x200
Control Registers
0x27F
0x280
0x2BF
0x2C0
0x2FF
0x300
Security Key FIFO
Reserved
128 bytes
128 bytes
128 bytes
128 bytes
128 bytes
64 bytes
RX FIFO
144 bytes
0x38F
© 2010 Microchip Technology Inc.
Preliminary
DS39776C-page 13