PL130-07 Datasheet, PDF (6/16 Pages) Microchip Technology – High Speed Translator Buffer to LVCMOS

PL130-07
TABLE 2-1:
Pin Name
GND
V_DD
DRV_SEL
PIN FUNCTION TABLE
SOIC-8L TSSOP-8L QFN-16L
1, 3, 6
4, 7
8
3
1, 2, 4, 5,
9, 14, 15
1, 7
7, 10,
11, 12
2
13
CLK_IN
2
5
3
CLK_OUT
5
OE
N/A
8
8
4
16
Type
P
Ground.
Description
P
Power supply.
I
Drive Select input: ‘1’ for standard drive,
‘0’ for high drive output. Internal pull-up
(default is ‘1’).
I
Clock input signal. The frequency of this
signal will be reproduced at the output
(after translation to CMOS level).
O
CMOS clock output.
I
Output Enable. See Table 2-2.
TABLE 2-2: OE LOGIC TABLE
Part Number
PL130-07
PL130-07A
OE State
0
1 (default)
0 (default)
1
Output Buffer State
Tri-State
Active
Active
Tri-State
DS20005598A-page 6
 2016 Microchip Technology Inc.