EQCO62R20.3 Datasheet, PDF (6/34 Pages) Microchip Technology – EQCO62R20.3 6.25 Gbps Asymmetric Coax Equalizer

EQCO62R20.3/EQCO31R20.3
1.1.1 SDIp/SDIn
SDIp/SDIn together form a differential input pair. It is
the differential voltage between these pins that the
EQCO62R20 analyzes and adaptively equalizes for
signal level and frequency response. The equalizer
automatically detects and adapts to signals with
different edge rates, different attenuation levels and
different cable characteristics. Both SDIp and SDIn
inputs are terminated by 60Ω to VCC on-chip. For each
input, an external 15Ω resistor is required in series.
1.1.2 SDOp/SDOn
SDOp/SDOn together form a differential pair, outputting
the reconstructed far-end transmit signal. SDOp/SDOn
are terminated on-chip with 2x50Ω resistors.
1.1.3 LFI
LFI is the uplink input signal that will be transmitted on
the SDIp/SDIn pair. LFI must be a 1.2V LVTTL signal.
For 2.5V and 3.3V input swing, an external resistor is
needed in series at the input of the chip.
1.1.4 AmpR
AmpR is a VCC resistor that sets the transmit
amplitude of the uplink output driver. The typical
value for CoaXPress is R_amp = 1.2 kΩ for 130 mV
transmit amplitude.
1.1.5 RISER
RiseR is a VCC resistor that selects the rise/fall time of
the uplink output driver. The typical value for
CoaXPress is R_rise = 10 kΩ for rise/fall time of 11 ns.
If no R_amp and R_rise are placed, the LF driver is disabled.
DS60001302B-page 6
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