EQCO62R20.3 Datasheet, PDF (29/34 Pages) Microchip Technology – EQCO62R20.3 6.25 Gbps Asymmetric Coax Equalizer

EQCO62R20.3/EQCO31R20.3
TABLE E-6: GROUND PLANE POSITION OF Figure 2-5
GND Plane Coordinates
X
Y
VCC Plane Coordinates
X
a
-1.725
3.75
m
b
-1.725
-3
n
c
-2.25
-3
o
d
-2.25
-5.2
p
e
-0.425
-7
q
f
0.225
-7
r
g
1.65
-5.575
h
1.65
-3
i
2.85
-3
j
2.85
-10.075
k
-0.9
-8.8
s
l
0.75
-10.45
t
-2.3
-2.3
1.75
1.75
2.85
2.85
-0.9
0.75
Y
-3.475
-6.65
-6.65
-5.575
-5.575
-10.075
-8.8
-10.45
FIGURE E-4: TRACK WIDTHS OF Figure 2-5
Track
Width
1
2
3
4
5
6
7
8
9
10
11
Note 1:
0.3
QFN.1; QFN.4 (GND)
0.3
QFN.2 (SDIp)
0.3
QFN.3 (SDIn)
0.2
QFN.5 (LFin)
0.2
QFN.6 (ampR)
0.2
QFN.7 (riseR)
0.3
100Ω Diff.⁽¹⁾
QFN.9; QFN.12 (GND)
QFN.10-11 (SDIp-SDIn)
0.5
QFN.13; QFN.16 (VCC)
0.5
C9; C10; C5
0.4
C1; C2
Width and spaces between lines need to be calculated based on PCB layer stack. Impedance should be
100Ω differential.
FIGURE E-5: USED LAYER STACK
 2012-2016 Microchip Technology Inc.
DS60001302B-page 29