EQCO62R20.3 Datasheet, PDF (10/34 Pages) Microchip Technology – EQCO62R20.3 6.25 Gbps Asymmetric Coax Equalizer

EQCO62R20.3/EQCO31R20.3
Ferrite Beads Fb1 and Fb2 (FBMH1608HM102 from
Taiyo Yuden) and inductor L1 (1812PS_103 from
Coilcraft [10 µH]) are recommended for CoaXPress.
For other applications, the inductor value can be larger,
leading to a physical larger inductor.
Connector BNC1 (75Ω right angle BNC C-SX-090 from
Cambridge) is recommended for CoaXPress.
Other inductors/ferrite beads/BNC connectors can
possibly be used, however, they must be selected
carefully for their RF-performance, since performance
can decrease significantly.
2.1 Guidelines for PCB Layout
When using the EQCO62T/R20 chipset at its full
purpose, i.e. including low-speed uplink and power
supply transmission, it is important not to disturb the
RF-performance of the high-speed downlink channel.
Implementing the circuit illustrated in Figure 2-1 with a
different PCB layout will in first instance not deliver full
data sheet performance. The simplest way of meeting
optimal performance, including jitter and return-loss
requirements, is to precisely follow the component and
layout recommendations. Note that at multi-gigabit
speeds, using "equivalent" components or small PCB
layout changes (even moving a via) can have
significant detrimental effects.
The easiest way for achieving the requirements of the
CoaXPress 1.1 specification is to use the recommended
circuits, components and layout illustrated in Figure 2-1.
For easy implementation, Microchip will provide the
Gerber file. Please ask for it by email.
Note: Email address: [e-mail]
2.1.1 RIGHT ANGLE BNC
Figure 2-2 below shows the four layers of the
recommended footprint for the EQCO62R20.3 chip
and the off-chip components that are critical for the
RF-performance of the system.
FIGURE 2-2:
RECOMMENDED PCB LAYOUT FOR EQCO62R20.3
In this layout, the size of the PCB area needed for the
chip is minimized. Approximately two times the BNC
footprint area is required for the full bidirectional
system: including the necessary elements for the
power transport.
DS60001302B-page 10
The differential output of the chip must be a 100Ω
differential transmission line. To minimize the parasitic
capacitance of the input pins, a cut-out of the ground
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