24AA64_02 Datasheet, PDF (6/24 Pages) Microchip Technology – 64K I2C™ Serial EEPROM

24AA64/24LC64
3.6 Device Addressing
A control byte is the first byte received following the
START condition from the master device (Figure 3-2).
The control byte consists of a four bit control code; for
the 24XX64 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24XX64 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 3-3). Because
only A12...A0 are used, the upper three address bits
are don’t care bits. The upper address bits are trans-
ferred first, followed by the less significant bits.
Following the START condition, the 24XX64 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX64 will select a read or
write operation.
FIGURE 3-2: CONTROL BYTE FORMAT
Read/Write Bit
Control Code
Chip Select
Bits
S 1 0 1 0 A2 A1 A0 R/W ACK
START Bit
Slave Address
Acknowledge Bit
3.7 Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 512K bits by
adding up to eight 24XX64's on the same bus. In this
case, software can use A0 of the control byte as
address bit A13, A1 as address bit A14, and A2 as
address bit A15. It is not possible to sequentially read
across device boundaries.
FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
ADDRESS HIGH BYTE
1
0
1
0
A
2
A
1
A
0
R/W
CONTROL
CODE
CHIP
SELECT
BITS
X
X
X
AA _A
12 11 10
A
9
A
8
ADDRESS LOW BYTE
A
7
•
•
•
•
•
•
A
0
X = Don’t Care Bit
DS21189F-page 6
 2002 Microchip Technology Inc.