PIC16F72 Datasheet, PDF (58/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter

PIC16F72
10.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Reference Manual,
(DS33023). In general, however, given a max of 10 kΩ
and at a temperature of 100°C, TACQ will be no more
than 16 µs.
10.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.0 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
• 2 TOSC
• 8 TOSC
• 32 TOSC
• Internal RC oscillator (2 - 6 µs)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
as small as possible, but no less than 1.6 µs and not
greater than 6.4 µs.
Table 10-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
10.3 Configuring Analog Port Pins
The ADCON1, and TRISA registers control the opera-
tion of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins), may cause the input buffer to
consume current out of the device
specification.
10.4 A/D Conversions
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2 TAD wait
is required before the next acquisition is started. After
this 2 TAD wait, an acquisition is automatically started
on the selected channel. The GO/DONE bit can then
be set to start the conversion.
TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS<1:0>
Max.
2 TOSC
00
1.25 MHz
8 TOSC
01
5 MHz
32 TOSC
RC^{(1, 2)}
10
20 MHz
11
(Note 1)
Note 1: The RC source has a typical TAD time of 4 µs, but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
DS39597B-page 56
 2002 Microchip Technology Inc.