PIC16F72 Datasheet, PDF (21/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter

2.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note, “Implementing a Table Read"
(AN556).
2.3.2 STACK
The stack allows a combination of up to eight program
calls and interrupts to occur. The stack contains the
return address from this branch in program execution.
Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSH’d onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POP’d in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSH’d or
POP’d.
After the stack has been PUSH’d eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on). An example of the overwriting of the stack is
shown in Figure 2-4.
FIGURE 2-4:
STACK MODIFICATION
Stack
Push1 Push9
Push2 Push10
Push3
Push4
Push5
Push6
Push7
Push8
Top-of-Stack
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
PIC16F72
2.4 Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper two bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. If a return from a CALL instruction
(or interrupt) is executed, the entire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PCLATH<4:3> bits is not required for the return
instructions (which POPs the address from the stack).
Note:
The PIC16F72 device ignores the paging
bit PCLATH<4:3>. The use of
PCLATH<4:3> as a general purpose read/
write bit is not recommended, since this
may affect upward compatibility with future
products.
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: INDIRECT ADDRESSING
NEXT
CONTINUE
movlw
movwf
clrf
incf
btfss
goto
:
0x20 ;initialize pointer
FSR ;to RAM
INDF ;clear INDF register
FSR ;inc pointer
FSR,4 ;all done?
NEXT ;NO, clear next
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-5.
 2002 Microchip Technology Inc.
DS39597B-page 19