PIC16F72 Datasheet, PDF (48/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter

PIC16F72
FIGURE 9-1:
SSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
RC4/SDI/SDA
RC5/SDO
SSPSR reg
bit0
Shift
Clock
RA5/AN4/SS
SS Control
Enable
Edge
Select
2
Clock Select
RC3/SCK/
SCL
SSPM3:SSPM0
4
TMR2 Output
2
Edge
Select
TRISC<3>
Prescaler TCY
4, 16, 64
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register)
appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
be configured such that RA5 is a digital I/O
.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is
set to VDD.
2: If the SPI is used in Slave mode with
CKE = ‘1’, then the SS pin control must be
enabled.
TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
0Bh,8Bh INTCON
10Bh,18Bh
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
0Ch
PIR1
— ADIF
—
— SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000
8Ch
PIE1
— ADIE
—
— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
85h
TRISA
—
— PORTA Data Direction Register
--11 1111 --11 1111
94h
SSPSTAT
—
—
D/A
P
S
R/W
UA
BF --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
DS39597B-page 46
 2002 Microchip Technology Inc.