PIC16F72 Datasheet, PDF (25/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter

3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
EXAMPLE 3-2:
BANKSEL PORTB
CLRF
PORTB
BANKSEL TRISB
MOVLW 0xCF
MOVWF TRISB
INITIALIZING PORTB
; Select bank for PORTB
; Initialize PORTB by
; clearing output
; data latches
; Select Bank for TRISB
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset.
FIGURE 3-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
RBPU⁽¹⁾
Data
Bus
WR
Port
WR
TRIS
Data Latch
DQ
CK
TRIS Latch
DQ
CK
VDD
VDD
P Weak
Pull-up
I/O pin
VSS
TTL
Input
Buffer
RD TRIS
QD
RD Port
EN
RB0/INT
RD Port
Schmitt Trigger
Buffer
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION<7>).
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
 2002 Microchip Technology Inc.
PIC16F72
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’d together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION<6>).
FIGURE 3-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
RBPU⁽¹⁾
Data
Bus
WR
Port
Data Latch
DQ
CK
VDD
VDD
P Weak
Pull-up
I/O pin
WR
TRIS
TRIS Latch
DQ
CK
TTL
Input
Buffer
VSS
ST
Buffer
RD TRIS
Latch
QD
RD Port
Set RBIF
EN
Q1
From Other
RB7:RB4 Pins
QD
EN
RB7:RB6 in Serial Programming Mode
RD Port
Q3
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION<7>).
DS39597B-page 23