LAN8710A Datasheet, PDF (50/82 Pages) SMSC Corporation – Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR Technology

Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR^® Technology
Datasheet
Chapter 4 Register Descriptions
4.1
This chapter describes the various control and status registers (CSR’s). All registers follow the IEEE
802.3 (clause 22.2.4) management register set. All functionality and bit definitions comply with these
standards. The IEEE 802.3 specified register index (in decimal) is included with each register definition,
allowing for addressing of these registers via the Serial Management Interface (SMI) protocol.
Register Nomenclature
Table 4.1 describes the register bit attribute notation used throughout this document.
Table 4.1 Register Bit Types
REGISTER BIT TYPE
NOTATION
R
W
RO
WO
WC
WAC
RC
LL
LH
SC
SS
RO/LH
NASR
RESERVED
REGISTER BIT DESCRIPTION
Read: A register or bit with this attribute can be read.
Read: A register or bit with this attribute can be written.
Read only: Read only. Writes have no effect.
Write only: If a register or bit is write-only, reads will return unspecified data.
Write One to Clear: writing a one clears the value. Writing a zero has no effect
Write Anything to Clear: writing anything clears the value.
Read to Clear: Contents is cleared after the read. Writes have no effect.
Latch Low: Clear on read of register.
Latch High: Clear on read of register.
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no
effect. Contents can be read.
Self-Setting: Contents are self-setting after being cleared. Writes of one have no
effect. Contents can be read.
Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After
it is read, the bit will either remain high if the high condition remains, or will go low if
the high condition has been removed. If the bit has not been read, the bit will remain
high regardless of a change to the high condition. This mode is used in some Ethernet
PHY registers.
Not Affected by Software Reset. The state of NASR bits do not change on assertion
of a software reset.
Reserved Field: Reserved fields must be written with zeros to ensure future
compatibility. The value of reserved bits is not guaranteed on a read.
Many of these register bit notations can be combined. Some examples of this are shown below:
„ R/W: Can be written. Will return current setting on a read.
„ R/WAC: Will return current setting on a read. Writing anything clears the bit.
Revision 1.4 (08-23-12)
50
DATASHEET
SMSC LAN8710A/LAN8710Ai