PIC18F4680 Datasheet, PDF (479/484 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
Parallel Slave Port (PSP) Write ............................... 145
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 184
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 184
PWM Direction Change ........................................... 181
PWM Direction Change at Near
100% Duty Cycle ............................................. 181
PWM Output ............................................................ 169
Repeat Start Condition ............................................. 216
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 438
Send Break Character Sequence ............................ 241
Slave Synchronization ............................................. 193
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) ......................................... 192
SPI Mode (Slave Mode with CKE = 0) ..................... 194
SPI Mode (Slave Mode with CKE = 1) ..................... 194
Stop Condition Receive or Transmit Mode .............. 220
Synchronous Reception
(Master Mode, SREN) ..................................... 244
Synchronous Transmission ...................................... 242
Synchronous Transmission (Through TXEN) .......... 243
Time-out Sequence on POR w/PLL
Enabled (MCLR Tied to VDD) ............................. 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ....................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ....................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 46
Timer0 and Timer1 External Clock .......................... 439
Transition for Entry to Idle Mode ................................ 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-speed Start-up
(INTOSC to HSPLL) ........................................ 354
Transition for Wake from Idle to Run Mode ............... 38
Transition for Wake from Sleep (HSPLL) ................... 37
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
Timing Diagrams and Specifications ................................ 435
A/D Conversion Requirements ................................ 452
AC Characteristics
Internal RC Accuracy ....................................... 436
Capture/Compare/PWM Requirements ................... 440
CLKO and I/O Requirements ................................... 437
EUSART Synchronous Receive
Requirements .................................................. 450
EUSART Synchronous Transmission
Requirements .................................................. 450
Example SPI Mode Requirements
Master Mode, CKE = 0 .................................... 442
Master Mode, CKE = 1 .................................... 443
Slave Mode, CKE = 0 ...................................... 444
Slave Mode, CKE = 1 ...................................... 445
External Clock Requirements .................................. 435
High/Low-Voltage Detect Characteristics ................ 432
I²C Bus Data Requirements (Slave Mode) .............. 447
Master SSP I²C Bus Data Requirements ................ 449
Master SSP I²C Bus Start/Stop
Bits Requirements ........................................... 448
Parallel Slave Port Requirements
(PIC18F4585/4680) ......................................... 441
PLL Clock ................................................................ 436
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Power-up Timer and
Brown-out Reset Requirements ...................... 438
Timer0 and Timer1 External
Clock Requirements ........................................ 439
Top-of-Stack Access .......................................................... 62
TRISE Register
PSPMODE Bit ......................................................... 138
TSTFSZ ........................................................................... 401
Two-Speed Start-up ................................................. 343, 354
Two-Word Instructions
Example Cases ......................................................... 66
TXSTA Register
BRGH Bit ................................................................. 231
V
Voltage Reference Specifications .................................... 431
W
Watchdog Timer (WDT) ........................................... 343, 352
Associated Registers ............................................... 353
Control Register ....................................................... 352
During Oscillator Failure .......................................... 355
Programming Considerations .................................. 352
WCOL ...................................................... 215, 216, 217, 220
WCOL Status Flag ................................... 215, 216, 217, 220
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 401
XORWF ........................................................................... 402
 2004 Microchip Technology Inc.
Preliminary
DS39625B-page 477