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PIC18F4680 Datasheet, PDF (381/484 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology | |||
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PIC18F2585/2680/4585/4680
CPFSGT
Compare f with W, Skip if f > W
Syntax:
CPFSGT f {,a}
Operands:
0 ⤠f ⤠255
a â [0,1]
Operation:
(f) â (W),
skip if (f) > (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110 010a ffff ffff
Description:
Compares the contents of data memory
location âfâ to the contents of the W by
performing an unsigned subtraction.
If the contents of âfâ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank (default).
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ⤠95 (5Fh). See
Section 25.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
If skip:
Q2
Read
register âfâ
Q3
Process
Data
Q4
No
operation
Q1
Q2
Q3
No
No
No
operation operation operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation operation operation
No
No
No
operation operation operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC
=
W
=
After Instruction
If REG
>
PC
=
If REG
â¤
PC
=
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
CPFSLT
Compare f with W, Skip if f < W
Syntax:
CPFSLT f {,a}
Operands:
0 ⤠f ⤠255
a â [0,1]
Operation:
(f) â (W),
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110 000a ffff ffff
Description:
Compares the contents of data memory
location âfâ to the contents of W by
performing an unsigned subtraction.
If the contents of âfâ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank (default).
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
If skip:
Q2
Read
register âfâ
Q3
Process
Data
Q4
No
operation
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
=
W
=
After Instruction
If REG
<
PC
=
If REG
â¥
PC
=
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
 2004 Microchip Technology Inc.
Preliminary
DS39625B-page 379
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