PIC18F4680 Datasheet, PDF (478/484 Pages) Microchip Technology – Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2585/2680/4585/4680
Operation in Power Managed Modes ...................... 195
Serial Clock .............................................................. 187
Serial Data In ........................................................... 187
Serial Data Out ........................................................ 187
Slave Mode .............................................................. 193
Slave Select ............................................................. 187
Slave Select Synchronization .................................. 193
SPI Clock ................................................................. 192
Typical Connection .................................................. 191
SS .................................................................................... 187
SSPOV ............................................................................. 217
SSPOV Status Flag .......................................................... 217
SSPSTAT Register
R/W Bit ............................................................. 200, 201
Stack Full/Underflow Resets .............................................. 64
Status Register ................................................................... 87
SUBFSR ........................................................................... 407
SUBFWB .......................................................................... 396
SUBLW ............................................................................ 397
SUBULNK ........................................................................ 407
SUBWF ............................................................................ 397
SUBWFB .......................................................................... 398
SWAPF ............................................................................ 398
T
Table Pointer Operations (table) ........................................ 98
Table Reads/Table Writes .................................................. 64
TBLRD ............................................................................. 399
TBLWT ............................................................................. 400
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 147
Associated Registers ............................................... 149
Clock Source Edge Select (T0SE Bit) ...................... 148
Clock Source Select (T0CS Bit) ............................... 148
Operation ................................................................. 148
Overflow Interrupt .................................................... 149
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 148
Timer1 .............................................................................. 151
16-Bit Read/Write Mode ........................................... 153
Associated Registers ............................................... 155
Interrupt .................................................................... 154
Operation ................................................................. 152
Oscillator .................................................................. 153
Layout Considerations ..................................... 154
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 154
Special Event Trigger (ECCP1) ............................... 174
Use as a Real-Time Clock ....................................... 154
Timer2 .............................................................................. 157
Associated Registers ............................................... 158
Interrupt .................................................................... 158
Operation ................................................................. 157
Output ...................................................................... 158
PR2 Register .................................................... 169, 175
TMR2 to PR2 Match Interrupt .......................... 169, 175
Timer3 .............................................................................. 159
16-Bit Read/Write Mode ........................................... 161
Associated Registers ............................................... 161
Operation ................................................................. 160
Oscillator .................................................. 151, 159, 161
Overflow Interrupt .................................... 151, 159, 161
Special Event Trigger (CCP) .................................... 161
TMR3H Register .............................................. 151, 159
TMR3L Register ............................................... 151, 159
Timing Diagrams
A/D Conversion ........................................................ 452
Acknowledge Sequence .......................................... 220
Asynchronous Reception ......................................... 239
Asynchronous Transmission .................................... 237
Asynchronous Transmission
(Back to Back) ................................................. 237
Automatic Baud Rate Calculation ............................ 235
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 240
Auto-Wake-up Bit (WUE) During Sleep ................... 240
Baud Rate Generator with Clock Arbitration ............ 214
BRG Overflow Sequence ......................................... 235
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 223
Brown-out Reset (BOR) ........................................... 438
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 224
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 224
Bus Collision During a Start Condition
(SCL = 0) ......................................................... 223
Bus Collision During a Start Condition
(SDA Only) ...................................................... 222
Bus Collision During a Stop Condition
(Case 1) ........................................................... 225
Bus Collision During a Stop Condition
(Case 2) ........................................................... 225
Bus Collision for Transmit and Acknowledge .......... 221
Capture/Compare/PWM (CCP) ............................... 440
CLKO and I/O .......................................................... 437
Clock Synchronization ............................................. 207
Clock/Instruction Cycle .............................................. 65
EUSART Synchronous Receive
(Master/Slave) ................................................. 450
EUSART Synchronous Transmission
(Master/Slave) ................................................. 450
Example SPI Master Mode (CKE = 0) ..................... 442
Example SPI Master Mode (CKE = 1) ..................... 443
Example SPI Slave Mode (CKE = 0) ....................... 444
Example SPI Slave Mode (CKE = 1) ....................... 445
External Clock (All Modes Except PLL) ................... 435
Fail-Safe Clock Monitor ........................................... 356
First Start Bit Timing ................................................ 215
Full-Bridge PWM Output .......................................... 179
Half-Bridge PWM Output ......................................... 178
High/Low-Voltage Detect ......................................... 270
I²C Bus Data ............................................................ 446
I²C Bus Start/Stop Bits ............................................ 446
I²C Master Mode (7 or 10-Bit Transmission) ........... 218
I²C Master Mode (7-Bit Reception) .......................... 219
I²C Slave Mode (10-Bit Reception,
SEN = 0) .......................................................... 204
I²C Slave Mode (10-Bit Reception,
SEN = 1) .......................................................... 209
I²C Slave Mode (10-Bit Transmission) .................... 205
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 202
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 208
I²C Slave Mode (7-Bit Transmission) ...................... 203
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 210
Master SSP I²C Bus Data ........................................ 448
Master SSP I²C Bus Start/Stop Bits ........................ 448
Parallel Slave Port (PIC18F4585/4680) ................... 441
Parallel Slave Port (PSP) Read ............................... 145
DS39625B-page 476
Preliminary
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